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description the LCX009AK is a 1.8cm diagonal active matrix tft-lcd panel addressed by the polycrystalline silicon super thin film transistors with built-in peripheral driving circuit. this panel provides full- color representation in ntsc/pal mode. rgb dots are arranged in a delta pattern featuring high picture quality of no fixed color patterns, which is inherent in vertical stripes and mosaic pattern arrangements. features the number of active dots: 180,000 (0.7-inch; 1.8cm in diagonal) horizontal resolution: 400 tv lines high optical transmittance: 3.5% (typ.) high contrast ratio with normally white mode: 200 (typ.) built-in h and v driving circuit (built-in input level conversion circuit, ttl drive possible) high quality picture representation with rgb delta arranged color filters full-color representation ntsc/pal compatible right/left inverse display function element structure dots total dots : 827 (h) 228 (v) = 188,556 active dots : 800 (h) 225 (v) = 180,000 built-in peripheral driving circuit using the polycrystalline silicon super thin film transistors. ?1 LCX009AK e94212c64-ps 1.8cm (0.7-inch) ntsc/pal color lcd panel sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
?2 LCX009AK block diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 h shift register h level shifter v level shifter v shift register c s lc com pad vv dd v ss vst vck2 vck1 en clr rgt hst hck2 hck1 hv dd blue red green com
?3 LCX009AK absolute maximum ratings (vss = 0v) h driver supply voltage hv dd ?.0 to +17 v v driver supply voltage vv dd ?.0 to +17 v h driver input pin voltage hst, hck1, hck2 ?.0 to +17 v rgt v driver input pin voltage vst, vck1, vck2 ?.0 to +17 v clr, en video signal input pin voltage green, red, blue ?.0 to +15 v operating temperature topr ?0 to +70 ? storage temperature tstg ?0 to +85 ? operating conditions (vss = 0v) supply voltage hv dd 13.5 0.5 v vv dd 13.5 0.5 v input pulse voltage (vp-p of all input pins except video signal input pins) vin 3.0v or more pin description pin no. 1 2 3 4 5 6 7 8 com green red blue hv dd hck1 hck2 hst common voltage of panel video signal (g) to panel video signal (r) to panel video signal (b) to panel power supply for h driver clock pulse for h shift register drive clock pulse for h shift register drive start pulse for h shift register drive 9 10 11 12 13 14 15 16 rgt clr en vck1 vck2 vst vss vv dd drive direction pulse for h shift register (h: normal, l: reverse) improvement pulse for uniformity enable pulse for gate selection clock pulse for v shift register drive clock pulse for v shift register drive start pulse for v shift register drive gnd (h, v drivers) power supply for v driver symbol description pin no. symbol description
?4 LCX009AK input equivalent circuit to prevent static charges, protective diodes are provided for each pin except the power supply. in addition, protective resistors are added to all pins except video signal input. the equivalent circuit of each input pin is shown below. (the resistor value: typ.) input 1m w lc level conversion circuit (single-phase input) 2.5k w 2.5k w vv dd input vv dd 2.5k w 2.5k w 1k w 1k w level conversion circuit (2-phase input) vck1 vck2 level conversion circuit (single-phase input) 2.5k w 2.5k w hv dd input level conversion circuit (single-phase input) 250 w 250 w hv dd input hv dd 250 w 250 w 250 w 250 w level conversion circuit (2-phase input) hck1 hck2 input hv dd from h driver signal line (1) video signal input (2) hck1, hck2 (3) hst (4) rgt (5) vck1, vck2 (6) vst, clr, en (7) com
?5 LCX009AK level conversion circuit the LCX009AK has a built-in level conversion circuit in the clock input unit located inside the panel. the circuit voltage is stepped up to 13.5v. this level conversion circuit meets the specifications of a 3.0v to 5.0v power supply of the externally-driven ic mainly. however, this circuit can operate even with a 12v power supply of the ic. 1. i/o characteristics of level conversion circuit (for a single-phase input unit) an example of the i/o voltage characteristics of a level conversion circuit is shown in the figure to the right. the input voltage value that becomes half the output voltage (after voltage conversion) is defined as vth. the vth value varies depending on the hv dd and vv dd voltages. the vth values under standard conditions are indicated in the table below. (hst, vst, en, clr, and rgt in the case of a single-phase input) hv dd = vv dd = 13.5v hv dd hv dd 2 vth input voltage [v] example of single-phase i/o characteristics output voltage (inside panel) item vth voltage of circuit vth 0.35 1.50 2.70 v symbol min. typ. max. unit (for a differential input unit) an example of i/o voltage characteristics of a level conversion circuit for a differential input is shown in the figure to the right. although the characteristics, including those of the vth voltage, are basically the same as those for a single- phased input, the two-phased input phase is defined. (refer to clock timing conditions.) hv dd hv dd 2 vth input voltage [v] example of differential i/o characteristics output voltage (inside panel) 2. current characteristics at the input pin of level conversion circuit a slight pull-in current is generated at the input pin of the level conversion circuit. (the equivalent circuit diagram is shown to the right.) the current volume increases as the voltage at the input pin decreases, and is maximized when the pin is grounded.) (electrical characteristics are defined by the grounded input.) v dd output hck1 input hck2 input level conversion equivalent circuit 0 0 max. value input pin voltage [v] 10 pull-in current characteristics at the input pin input pin current
?6 LCX009AK input signals 1. input signal voltage conditions (vss = 0v) item h driver input voltage (low) (high) (low) (high) vhil vhih vvil vvih vvc vsig vcom ?.3 3.0 ?.3 3.0 5.8 vvc ?4.5 vvc ?0.55 0.0 5.0 0.0 5.0 6.0 vvc ?0.40 0.3 5.5 0.3 5.5 6.2 vvc + 4.5 vvc ?0.25 v v v v v v v v driver input voltage video signal center voltage video signal input range * 1 common voltage of panel symbol min. typ. max. unit * 1 video input signal should be symmetrical to vvc. 2. clock timing conditions (ta = 25?) hst rise time hst fall time hst data set-up time hst data hold time hckn * 2 rise time hckn * 2 fall time hck1 fall to hck2 rise time hck1 rise to hck2 fall time clr rise time clr fall time clr pulse width clr fall to hst rise time vst rise time vst fall time vst data set-up time vst data hold time vckn * 2 rise time vckn * 2 fall time vck1 fall to vck2 rise time vck1 rise to vck2 fall time en rise time en fall time vck2 rise to en fall time vck1 rise to en rise time trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck trclr tfclr twclr tohst trvst tfvst tdvst thvst trvckn tfvckn to1vck to2vck tren tfen tdvck2 tdvck1 ?00 ?00 ?5 ?5 3400 1850 ?0 ?0 ?0 ?0 ?0 ?0 60 ?20 0 0 3500 1950 32 ?2 0 0 0 0 30 30 100 ?0 30 30 15 15 100 100 3600 2050 100 100 50 ?0 100 100 20 20 100 100 20 20 ns ? ns item symbol min. typ. max. unit hst hck clr vst vck en * 2 hckn and vckn mean hck1, hck2 and vck1, vck2. (fhckn = 2.75mhz, fvckn = 7.81khz)
?7 LCX009AK hst rise time hst hck clr hst fall time hst data set-up time hst data hold time hckn* 2 rise time hckn* 2 fall time hck1 fall to hck2 rise time hck1 rise to hck2 fall time clr rise time clr fall time clr pulse width clr fall to hst rise time hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns tdhst = 60ns thhst = ?20ns tdhst = 60ns thhst = ?20ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns hckn * 2 duty cycle 50% to1hck = 0ns to2hck = 0ns trhst tfhst tdhst thhst trhckn tfhckn to1hck to2hck trclr tfclr twclr tohst item symbol waveform conditions 90% 10% 10% 90% hst trhst tfhst 50% 50% * 3 hst hck1 tdhst thhst 50% 50% * 2 hckn 10% 10% 90% 90% trhckn tfhckn 50% 50% * 3 hck1 to2hck to1hck 50% 50% hck2 clr 90% 90% 10% 10% trclr tfclr clr 50% 50% 50% twclr tohst hst
?8 LCX009AK vst rise time vst vck en vst fall time vst data set-up time vst data hold time vckn* 2 rise time vckn* 2 fall time vck1 fall to vck2 rise time vck1 rise to vck2 fall time en rise time en fall time vck2 rise to en fall time vck1 rise to en rise time vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns tdvst = 32s thvst = ?2s tdvst = 32s thvst = ?2s vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns vckn * 2 duty cycle 50% to1vck = 0ns to2vck = 0ns trvst tfvst tdvst thvst trvckn tfvckn to1vck to2vck tren tfen tdvck2 tdvck1 90% 10% 10% 90% vst trvst tfvst 50% 50% * 3 vst vck1 tdvst thvst 50% 50% vckn 10% 10% 90% 90% trvckn tfvckn 50% 50% * 3 vck1 to2vck to1vck 50% 50% vck2 90% 90% 10% 10% tfen tren 50% 50% * 3 vck2 tdvck2 tdvck1 50% 50% en en * 3 definitions: the right-pointing arrow ( ) means +. the left-pointing arrow ( ) means ? the black dot at an arrow ( ) indicates the start of measurement. item symbol waveform conditions
?9 LCX009AK electrical characteristics 1. horizontal drivers (ta = 25?, hv dd = 13.5v, vv dd = 13.5v) item input pin capacitance hckn hst input pin current hck1 hck2 hst rgt video signal input pin capacitance current consumption chckn chst ihck1 ihck2 ihst irgt csig ih hck1 = gnd hck2 = gnd hst = gnd rgt = gnd hckn: hck1, hck2 (2.75mhz) ?00 ?00 ?00 ?00 5 5 ?0 ?60 ?00 ?5 45 3 10 10 60 4 pf pf ? ? ? ? pf ma symbol min. typ. max. unit condition 2. vertical drivers item input pin capacitance vckn vst input pin current vck1 vck2 vst en clr current consumption cvckn cvst ivck1 ivck2 ivst, ien, iclr iv ?00 ?00 ?00 5 5 ?0 ?00 ?5 400 10 10 1000 pf pf ? ? ? ? symbol min. typ. max. unit condition 3. total power consumption of the panel item total power consumption of the panel (ntsc) pwr 45 70 mw symbol min. typ. max. unit 4. com input resistance item com ?vss input resistance rcom 0.5 1 m symbol min. typ. max. unit vck1 = gnd vck2 = gnd vst, en, clr=gnd vckn: vck1, vck2 (7.87khz)
?10 LCX009AK electro-optical characteristics (ta = 25?, ntsc mode) item contrast ratio 25? 60? x y x y x y 25? 60? 25? 60? 25? 60? r vs. g b vs. g 0? 25? 0? 25? 60? 60min. cr 25 cr 60 t rx ry gx gy bx by v 90-25 v 90-60 v 50-25 v 50-60 v 10-25 v 10-60 v 50rg v 50bg ton0 ton25 toff0 toff25 f yt60 vcomopt 80 80 2.7 0.560 0.300 0.275 0.541 0.120 0.040 1.1 1.0 1.5 1.4 2.2 2.1 5.45 200 200 3.5 0.630 0.345 0.310 0.595 0.148 0.088 1.6 1.3 2.0 1.8 2.7 2.5 ?.10 0.10 25 8 65 20 5.60 0.670 0.390 0.347 0.650 0.187 0.122 2.2 2.1 2.5 2.4 3.2 3.1 ?.25 0.45 100 40 150 60 ?0 20 5.75 1 2 3 4 5 6 7 8 9 % cie standards v v ms db s v optical transmittance chromaticity r g b v 90 v 50 v 10 on time off time v ?t characteristics half tone color reproduction range response time flicker image retention time optimum vcom voltage symbol measurement method min. typ. max. unit
?11 LCX009AK

* measurement system i * measurement system ii lcd panel luminance meter measurement equipment light detector measurement equipment back light: color temperature 6500k, +0.004uv (25?) * back light spectrum (reference) is listed on another page. optical fiber lcd panel light receptor lens light source basic measurement conditions (1) driving voltage hv dd = 13.5v, vv dd = 13.5v vvc = 6.0v, vcom = 5.6v (2) measurement temperature 25? unless otherwise specified. (3) measurement point one point in the center of screen unless otherwise specified. (4) measurement systems two types of measurement system are used as shown below. (5) rgb input signal voltage (vsig) vsig = 6 v ac (v) (v ac : signal amplitude) back light 3.5mm drive circuit 1. contrast ratio contrast ratio (cr) is given by the following formula (1). cr = l (white) ... (1) l (black) l (white): surface luminance of the tft-lcd panel at the rgb signal amplitude v ac = 0.5v. l (black): surface luminance of the panel at v ac = 4.5v both luminosities are measured by system i .
?12 LCX009AK 2. optical transmittance optical transmittance (t) is given by the following formula (2). t = 100 (%) ... (2) l (white) is the same expression as defined in the 'contrast ratio' section. 3. chromaticity chromaticity of the panels are measured by system i . raster modes of each color are defined by the representations at the input signal amplitude conditions shown in the table below. system i uses chromaticity of x and y on the cie standards here. signal amplitudes (v ac ) supplied to each input r input g input b input raster r g b 0.5 4.5 4.5 4.5 0.5 4.5 4.5 4.5 0.5 (unit: v) 4. v ?t characteristics v ?t characteristics, the relationship between signal amplitude and the transmittance of the panels, are measured by system ii . v90, v50 and v10 correspond to the each voltage which defines 90%, 50% and 10% of transmittance respectively. 5. half tone color reproduction range half tone color reproduction range of the lcd panels is characterized by the differences between the v ?t characteristics of r, g and b. the differences of these v ?t characteristics are measured by system ii . system ii defines signal voltages of each r, g, b raster modes which correspond to 50% of transmittance, v 50r , v 50g and v 50b respectively. v 50rg and v 50bg , the voltage differences between v 50r and v 50g , v 50b and v 50g , are simply given by the following formula (3) and (4) respectively. v 50rg = v 50r ?v 50g ... (3) v 50bg = v 50b ?v 50g ... (4) 90 50 10 v 90 v 50 v 10 v ac ?signal amplitude [v] transmittance [%] 100 50 0 v 50r v 50b v 50g v ac ?signal amplitude [v] transmittance [%] v 50rg v 50bg g raster b raster r raster l (white) luminance of back light
?13 LCX009AK 6. response time response time t on and t off are defined by the formula (5) and (6) respectively. t on = t1 ?ton ... (5) t off = t2 ?toff ... (6) t1: time which gives 10% transmittance of the panel. t2: time which gives 90% transmittance of the panel. the relationships between t1, t2, ton and toff are shown in the right figure. 7. flicker flicker (f) is given by the formula (7). dc and ac (ntsc: 30hz, rms, pal: 25hz, rms) components of the panel output signal for gray raster * mode are measured by a dc voltmeter and a spectrum analyzer in system ii. ac component f (db) = 20log {} ... (7) dc component 8. image retention time image retention time is given by the following procedures: apply monoscope signal to the lcd panel for 60 minutes and then change monoscope signal * to gray scale signal (vsig = 6 v ac (v); v ac = 3 to 4v) so as to give the maximum image retention. hold input signal v ac . the time of the residual image to disappear gives the image retention time. * monoscope signal conditions: vsig = 6 4.5 or 6 2.0 (v) (shown in the right figure) vcom = 5.6v input signal 4.5v 0.5v 6v 0v light transmission output waveform 100% 90% 10% 0% ton t1 ton toff t2 toff * r, g, b input signal condition for gray raster mode is given by vsig = 6 v 50 (v) where:v 50 is the signal amplitude which gives 50% of transmittance in v ?t curve. black level white level vsig waveform 6v 0v 4.5v 2.0v 4.5v 2.0v
?14 LCX009AK 9. method of measuring the optimum vcom there are two methods of measuring the optimum vcom using the photoelectric element. 9-1. method of measuring flicker in the field invert drive mode, adjust the flicker level of the half tone (vsig = 1.5 to 2.5v) using the photoelectric element and oscilloscope so that its 30hz component becomes minimum. the vcom value at this time is taken to be the optimum vcom. 9-2. method of measuring contrast in the normal 1h invert drive mode, adjust the optical output voltage of the half tone (vsig = 1.5 to 2.5v) so that it becomes minimum. the vcom value at this time is taken to be the optimum vcom. example of back light spectrum (reference) 0.4 0.3 0.2 0.1 0 400 500 600 700 wave length 380 ?780 [nm]
?15 LCX009AK description of operation 1. color coding color filters are coded in a delta arrangement. the shaded area is used for the dark border around the display. b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r g r b g r b g r b g r b g r b g r b r g b r g b r g b r g b r g b r r b g r b g r b g r b g r b g r g gate sw dummy 1 to 4 gate sw dummy 5 to 8 gate sw gate sw gate sw gate sw active area photo-shielding 827 14 800 13 2 1 225 228
?16 LCX009AK 2. lcd panel operations a vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse to every 225 gate lines sequentially in every single horizontal scanning period. a vertical shift register scans the gate lines from the top to bottom of the panel. the selected pulse is delivered when the enable pin turns to high level. pal mode images are displayed by controlling the enable and vck1, vck2 pins. the enable pin should be high when not in use. a horizontal driver, which consists of horizontal shift registers, gates and cmos sample-and-hold circuit, applies selected pulses to every 800 signal electrodes sequentially in a single horizontal scanning period. scanning direction of horizontal shift register can be switched with rgt pin.scanning direction is left to right for rgt pin at high level; and right to left for rgt pin at low level.(these scanning directions are from a front view.) normally, set to high level. vertical and horizontal drivers address one pixel, and then dot thin film transistors (tfts; two tfts for one dot) turn on to apply a video signal to the dot. the same procedures lead to the entire 225 800 dots to display a picture in a single vertical scanning period. pixels are arranged in a delta pattern, where sets of rgb pixels are positioned with 1.5-dot offset against juxtaposed horizontal line. for this reason, 1.5-dot offset of a horizontal driver output pulse against horizontal synchronized pulse is required to apply a video signal to each dot properly. 1 h reversed displaying mode is required to apply video signal to the panel. the clr pin is provided to eliminate the shading effect caused by the coupling of selected pulses. while maintaining the clr at high level, the vv dd potential drops to approximately 8.5v. this pin should be grounded when not in use. the video signal must be input with polarity-inverted system in every horizontal cycle. timing diagrams of the vertical and the horizontal right-direction scanning (rgt = high level) display cycle are shown below. hck1 and hck2 should be exchanged to display the left-direction horizontal scanning (rgt = low level). this exchange enables the center of the image to be fixed by eliminating offsets. vertical display 225h (14.3ms) 1 2 224 225 (1) vertical display cycle vd vst vck1 vck2 horizontal display cycle (48.4s) 123 45 6 270 271 (2) horizontal display cycle (right-direction scanning) blk hst hck1 hck2 the horizontal display cycle consists of 800/3 = 267 clock pulses because of rgb simultaneous sampling * . * refer to description of operation "3. rgb simultaneous sampling''
?17 LCX009AK 3. rgb simultaneous sampling horizontal driver performs r, g and b signal sampling simultaneously, which requires the phase matching between r, g, b signals to prevent horizontal resolution from deteriorating. the phase matching by an external signal delaying circuit is needed before applying video signal to the lcd panel. two methods are applied for the delaying procedure: sample-and-hold and delay circuit. these two block diagrams are as follows. the lcx009 has a right/left inverse function. the following phase relationship diagram indicates the phase setting for the right-direction scanning (rgt = high level). for the left-direction scanning (rgt = low level), the phase setting should be inverted for b and g signals. (1) sample-and-hold (right-direction scanning) (right-direction scanning) s/h s/h ac amp s/h ac amp s/h ac amp s/h (2) delay circuit (right-direction scanning) delay delay ac amp delay ac amp ac amp 4 3 b r g blue red green ckb ckr ckg ckg ckg hckn ckb ckr ckg blue red green b r g LCX009AK LCX009AK 2 4 3 2
?18 LCX009AK example of color filter spectrum (reference) 400 500 600 700 wavelength [nm] transmittance [%] 0 20 40 60 80 100 b g r color filter spectrum
?19 LCX009AK color display system block diagram (1) an example of single-chip display system is shown below. y/color difference y/c lcd panel ntsc/pal LCX009AK cxa1854r red green blue hck1 hst vst hck2 vck1 en vck2 clr rgt (refer to cxd1845r data sheet.) composite video +12v +5v +13.5v vcom
?20 LCX009AK y/color difference y/c red green blue composite video lcd panel ntsc/pal LCX009AK decoder/driver cxa1785ar tg cxd2411r hck1 hst vst hck2 vck1 en vck2 clr rgt +5v frp sync +12v +5v +13.5v vcom (refer to cxd2411r data sheet.) color display system block diagram (2) an example of dual-chip display system is shown below.
?21 LCX009AK notes on handling (1) static charge prevention be sure to take following protective measures. tft-lcd panels are easily damaged by static charge. a) use non-chargeable gloves, or simply use bare hands. b) use an earth-band when handling. c) do not touch any electrodes of a panel. d) wear non-chargeable clothes and conductive shoes. e) install conductive mat on the working floor and working table. f) keep panels away from any charged materials. g) use ionized air to discharge the panels. (2) protection from dust and dirt a) operate in clean environment. b) when delivered, a surface of a panel (polarizer) is covered by a protective sheet. peel off the protective sheet carefully not to damage the panel. c) do not touch the surface of a panel. the surface is easily scratched. when cleaning, use a clean-room wiper with isopropyl alcohol. be careful not to leave stain on the surface. d) use ionized air to blow off dust at a panel. (3) other handling precautions a) do not twist or bend the flexible pc board especially at the connecting region because the board is easily deformed. b) do not drop a panel. c) do not twist or bend a panel or a panel frame. d) keep a panel away from heat source. e) do not dampen a panel with water or other solvents. f) avoid to store or to use a panel in high temperature or in high humidity, which results in panel damages.
?22 LCX009AK package outline unit: mm p 0.5 0.02 15 = 7.5 0.03 pin16 pin1 0.5 0.1 22.0 0.15 11.0 0.25 (14.4) 2.9 0.15 8.5 0.05 18.4 0.2 1.3 0.3 thickness of the connector 0.3 0.05 (10.7) 9.5 0.25 21.0 0.15 33.2 0.8 0.5 0.15 3.0 0.3 4-r1.0 electrode (enlarged) ck1 4.0 0.5 reinforcing board + 0.04 ?0.03 0.35 sc active area incident light description molding material outside frame reinforcing board reinforcing material polarizing film f p c no 1 2 3 4 5 6 weight 2g 1 2 3 4 5 6 6 active area

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